Design Automation Conerefence 2008

DAC is just a round the corner (June 8-13 in Anaheim). One of the things in the works is a "Birds of a Feather" session on consisting of EDA bloggers. Some of the subjects being proposed for discussion are:

• What is a blog (for those living under a rock)?
• What place has a blog in the EDA industry?
• What are some the issues involved in corporate blogging?

If you're reading this, and have any ideas for this discussion, want to paticipate, or just want to discuss it in general, head over to the main DFT Digest site, or to the blogs of others who are involved, such as Cool Verification or Harry the ASIC Guy.

JMF

DFT News - November 2007

Here's a wrap up of November's DFT-related news... for DFT talk and information go to DFT Digest or DFT Forum!

IIT team proposes joint approach for testing large SoC designs

GOEPEL electronic’s SCANFLEX® JTAG/Boundary Scan Platform now integrated into Aeroflex 5800 Series ATE System

Low-power design animates panel in Taiwan

SynTest Receives A Fundamental Patent on At-Speed Capture Invention for Scan ATPG

ECS research paper rated for industry impact

JTAG Technologies renowned JT 3705 Explorer goes USB

Perform Design-for-Test and Power Management at the RTL

Thinking out of the box: Expanding STC's impact with STIX (Guest commentary)

Free Calculator Determines ROI On PCB Design Software

Critical controller boards put on trial

Magma Named to Silicon Valley's Fastest-Growing Software & IT Companies in Deloitte's Technology Fast 50 Program for Fourth Consecutive Year

New SYSTEM CASCON™ Software Release Enhances In-System Programming and 3rd Party ATE Integration

XJTAG v2.0 boundary scan system sets new standard for PCB debug & test

DFT News - ITC Week 2007

The International Test Conference is now recent history - but here are a few related news items and press releases that have come out in the past week. For discussion and/or analysis, please visit DFT Digest or DFT Forum!

Intellitech Offers New Concurrent JTAG Test Platform for PCBs with ARM Based Processors

Panel explores the expanded role of test in DFM

Intel VP at ITC calls for test development advances to meet challenges of next-gen SoC

The Last Bastion II : Some Q&A with DeFacto President and CTO Dr. Chouki Aktouf

ATPG Tool Meets Growing Demand For Scan Test Compression

TI fellow defines conditions and requirements for adaptive test at ITC

LogicVision Common Stock Transferred to the Nasdaq Capital Market

LogicVision Reports Third Quarter 2007 Financial Results

DFT Microsystems Bolsters Executive Team

Synopsys Customers Accelerate Yield Learning With Converged Test and Yield Management Data Flow

International Test Conference Begins!

A couple more press releases for Day 3 of the International Test Conference (ITC). Today the technical program starts (yesterday and Sunday were filled with day-long tutorials). Go to the main DFT Digest site for some insight into what's happening, or add your two cents at the DFT Forum!

G2 Microsystems Innovates With Cadence Low-Power Solution for Faster Development of Wireless Devices

Aehr Test Systems Announces FOX-15(TM) Full Wafer Contact Test and Burn-In System

ASSET® Expands Next-Generation Embedded Instrumentation

Cadence Test Technology Helps LSI Corporation, Kawasaki Microelectronics Deliver Products Faster

Cadence Encounter Test Helps Enable IBM To Deliver High-volume Chips

Genesys Testware Adds Automated Batch-mode Diagnosis and Characterization of Embedded Memories

ITC Monday news...

Posting these as they come up...

DeFacTo Unveils New Design for Test Product that Eliminates Need for Gate-level Scan; Creates Industry’s First High-level DFT Sign-off Methodology

Synopsys Advances Low Power Management for Manufacturing Test

Synopsys Improves the Quality of Manufacturing Tests with Timing-Aware Pattern Generation

ITC month, weeks 2 and 3

A couple of things:

ITC Test week started today with tutorials. Hop on over to DFT Digest for additional coverage of this event.

Speaking of DFT Digest, there has begun a collaboration of sorts between DFT Digest and DFT Forum. DFT Digest will still try to present interesting DFT-related information, while DFT Forum will be the main place for DFT- and EDA-related real-time discussion. Please visit and register for both sites!

Now, following are some of the happenings in the DFT world for the second couple of weeks of October:

STC Releases First Draft of Terminology Specifications to Semiconductor Industry and Announces Activities at ITC

Magma Unveils Talus ATPG and Talus ATPG-X - Expands Design-for-Test Capabilities with Physically Aware ATPG and On-Chip Compression

Magma Partners with Inovys and Source III to Ensure Interoperability of Talus ATPG and Leading Testers

LogicVision Announces Industry's Most Comprehensive On-Chip eDRAM Test and Repair Solution

LogicVision Receives Letter From Nasdaq Regarding Noncompliance With Minimum Bid Price Rule

Perform Design-for-Test and Power Management at the RTL

Mentor Graphics Announces TestKompress Xpress Technology to Address Manufacturing Test Requirements for 65 and 45 Nanometer Integrated Circuits

More DFT in the News - 1st week of ITC Month!

LogicVision Announces Expanded and Worldwide Use of Embedded Test Solutions by NEC Electronics for SOC Designs

LogicVision's Embedded SerDes Test Selected by PLX Technology for Gen 2 PCI Express Device Family

Teseda Corporation Launches the V550