DFT Digest

Design Automation Conerefence 2008

2008-05-25T10:42:00.000-07:00

DAC is just a round the corner (June 8-13 in Anaheim). One of the things in the works is a "Birds of a Feather" session on consisting of EDA bloggers. Some of the subjects being proposed for discussion are:

What is a blog (for those living under a rock)?
What place has a blog in the EDA industry?
What are some the issues involved in corporate blogging?

If you're reading this, and have any ideas for this discussion, want to paticipate, or just want to discuss it in general, head over to the main DFT Digest site, or to the blogs of others who are involved, such as Cool Verification or Harry the ASIC Guy.

JMF

DFT News - November 2007

2007-11-25T19:42:00.000-08:00

Here's a wrap up of November's DFT-related news... for DFT talk and information go to DFT Digest or DFT Forum!

IIT team proposes joint approach for testing large SoC designs

GOEPEL electronic’s SCANFLEX® JTAG/Boundary Scan Platform now integrated into Aeroflex 5800 Series ATE System

Low-power design animates panel in Taiwan

SynTest Receives A Fundamental Patent on At-Speed Capture Invention for Scan ATPG

ECS research paper rated for industry impact

JTAG Technologies renowned JT 3705 Explorer goes USB

Perform Design-for-Test and Power Management at the RTL

Thinking out of the box: Expanding STC's impact with STIX (Guest commentary)

Free Calculator Determines ROI On PCB Design Software

Critical controller boards put on trial

Magma Named to Silicon Valley's Fastest-Growing Software & IT Companies in Deloitte's Technology Fast 50 Program for Fourth Consecutive Year

New SYSTEM CASCON™ Software Release Enhances In-System Programming and 3rd Party ATE Integration

XJTAG v2.0 boundary scan system sets new standard for PCB debug & test

DFT News - ITC Week 2007

2007-10-27T13:05:00.000-07:00

The International Test Conference is now recent history - but here are a few related news items and press releases that have come out in the past week. For discussion and/or analysis, please visit DFT Digest or DFT Forum!

Intellitech Offers New Concurrent JTAG Test Platform for PCBs with ARM Based Processors

Panel explores the expanded role of test in DFM

Intel VP at ITC calls for test development advances to meet challenges of next-gen SoC

The Last Bastion II : Some Q&A with DeFacto President and CTO Dr. Chouki Aktouf

ATPG Tool Meets Growing Demand For Scan Test Compression

TI fellow defines conditions and requirements for adaptive test at ITC

LogicVision Common Stock Transferred to the Nasdaq Capital Market

LogicVision Reports Third Quarter 2007 Financial Results

DFT Microsystems Bolsters Executive Team

Synopsys Customers Accelerate Yield Learning With Converged Test and Yield Management Data Flow

International Test Conference Begins!

2007-10-23T07:57:00.000-07:00

A couple more press releases for Day 3 of the International Test Conference (ITC). Today the technical program starts (yesterday and Sunday were filled with day-long tutorials). Go to the main DFT Digest site for some insight into what's happening, or add your two cents at the DFT Forum!

G2 Microsystems Innovates With Cadence Low-Power Solution for Faster Development of Wireless Devices

Aehr Test Systems Announces FOX-15(TM) Full Wafer Contact Test and Burn-In System

ASSET® Expands Next-Generation Embedded Instrumentation

Cadence Test Technology Helps LSI Corporation, Kawasaki Microelectronics Deliver Products Faster

Cadence Encounter Test Helps Enable IBM To Deliver High-volume Chips

Genesys Testware Adds Automated Batch-mode Diagnosis and Characterization of Embedded Memories

ITC Monday news...

2007-10-22T14:48:00.000-07:00

Posting these as they come up...

DeFacTo Unveils New Design for Test Product that Eliminates Need for Gate-level Scan; Creates Industry’s First High-level DFT Sign-off Methodology

Synopsys Advances Low Power Management for Manufacturing Test

Synopsys Improves the Quality of Manufacturing Tests with Timing-Aware Pattern Generation

ITC month, weeks 2 and 3

2007-10-21T16:50:00.000-07:00

A couple of things:

ITC Test week started today with tutorials. Hop on over to DFT Digest for additional coverage of this event.

Speaking of DFT Digest, there has begun a collaboration of sorts between DFT Digest and DFT Forum. DFT Digest will still try to present interesting DFT-related information, while DFT Forum will be the main place for DFT- and EDA-related real-time discussion. Please visit and register for both sites!

Now, following are some of the happenings in the DFT world for the second couple of weeks of October:

STC Releases First Draft of Terminology Specifications to Semiconductor Industry and Announces Activities at ITC

Magma Unveils Talus ATPG and Talus ATPG-X - Expands Design-for-Test Capabilities with Physically Aware ATPG and On-Chip Compression

Magma Partners with Inovys and Source III to Ensure Interoperability of Talus ATPG and Leading Testers

LogicVision Announces Industry's Most Comprehensive On-Chip eDRAM Test and Repair Solution

LogicVision Receives Letter From Nasdaq Regarding Noncompliance With Minimum Bid Price Rule

Perform Design-for-Test and Power Management at the RTL

Mentor Graphics Announces TestKompress Xpress Technology to Address Manufacturing Test Requirements for 65 and 45 Nanometer Integrated Circuits

More DFT in the News - 1st week of ITC Month!

2007-10-09T07:03:00.000-07:00

LogicVision Announces Expanded and Worldwide Use of Embedded Test Solutions by NEC Electronics for SOC Designs

LogicVision's Embedded SerDes Test Selected by PLX Technology for Gen 2 PCI Express Device Family

Teseda Corporation Launches the V550

Design-for-Test In the News

2007-10-03T10:14:00.000-07:00

A smattering of press releases and such for the last couple of months:

Westinghouse Rail Systems selects XJTAG boundary scan system to verify prototype integrity

Mentor Graphics Chairman and CEO to Present Keynote at International System-on-Chip Design Conference

Mentor's TestKompress reaches out to 45-nm

Mentor Graphics Announces TestKompress Xpress Technology to Address Manufacturing Test Requirements for 65 and 45 Nanometer Integrated Circuits

LogicVision Announces That Q3 2007 Cash Exceeds Guidance

Goepel’s Puri on North American restructuring

Dr. Jacob Abraham receives Best Paper Award at international conference

Global Unichip Adopts Synopsys Test Solution to Achieve Higher SoC Test Quality

Strategic Alliance Between GOEPEL Electronic And Testonica Lab

LogicVision Provides Desktop Silicon Characterization and Diagnostics Solution with the Introduction of Silicon Insight

Perform Design-for-Test and Power Management at the RTL

New Digital I/O Scan Test Module Provides Flexibility

International Test Conference -- The Cornerstone of Test Week(TM) Holds 38th Conference in Santa Clara, California, October 23-25, 2007

ITC tackles nanometer test challenges

Synopsys Lowers the Cost of Semiconductor Testing at Tessolve

Cost-Effective, Ultra-High-Quality Test Results Using Synopsys DFT MAX Achieved at SHARP

ARM Selects XJTAG For RealView Development Tools Debug And Test

LogicVision Announces New Release of Its Embedded SerDes Test Solution

SynTest granted 6 more Patents since October 2006

DFT News - Late June '07

2007-07-10T22:03:00.000-07:00

Here are some items from the last two weeks of June 2007 - Check out DFT Digest - The Real DFT for other discussion of Design for Test related subjects!

6/28/07 - ISS Group - LogicVision Customer Training, July 25-26 - Hmmm... I could use a vacation to Sweden!!!

6/27/07 - Technotime Integrates XJTAG Boundary Scan into Novel PCB Test Solution - Always a lot going on in the board test world...

6/26/07 - ATE group to devise interface standards - Standardization in the ATE community is as difficult as it is in the EDA world!

6/21/07 - Design for debugging: the unspoken imperative in chip design - To hell with test, design for debugging!!

6/20/07 - Designing "with" instead of "for" - Cadence is really pushing for designing "with" test, instead of "for" test. They have a point...

6/20/07 - Corelis Adds Boundary-Scan Scripting Support to its ScanExpress ... - a new feature that enables the user to create customized testing sessions.

6/20/07 - Boundary-scan development software continues to advance - JTAG Technology's Provision

6/18/07 - Inovys Achieves Top Ranking for Excellence in Customer Satisfaction - Inovys provides innovative yield enhancement, failure analysis, and design debug solutions for the semiconductor industry. Need to write up something at the main site on these guys...

Where Am I? DFT in the News - June 12th 2007

2007-06-12T15:07:00.000-07:00

I'm overwhelmed - I've just been so busy, I've only been able to post the bare minimum over at DFT Digest

However, here's what I've collected over the last couple of weeks, and I promise to keep it up.

6/12/07 - Mentor Graphics Acquires Sierra Design Automation
Not strictly DFT, but, it's Mentor...

6/8/07 - Panelists identify DFM problems, solutions
Yes, DFM... the favorite topic of every EDA conference this year.

6/7/07 - DAC 2007: low-power SoC design takes on a new meaning
And this was the second favorite subject this year at DAC.

6/6/07 - New boundary scan controller from Goepel
The board test realm.

6/6/07 - Vendors pursue new DFT strategies
Here's the grand total of what design-for-test was at DAC.

6/5/07 - Mentor Collaborates with TSMC
DFM Capabilities in Reference Flow 8.0

6/4/07 - Synopsys announces advanced Techniques in TSMC Reference flow 8.0
Ooooh... TSMC Reference Flow 8.0 trifecta in play!

6/4/07 - Cadence accelerates 45-nm design with TSMC Reference Flow 8.0
Trifecta complete!

Done for now... check back later!

Design-for-Test News - Week 3, March 2007

2007-03-20T22:19:00.000-07:00

Here's a wrap up of some news items that have come across my desk this week. If you want to explore some 'off-the-beaten-track' issues regarding DFT - go to DFT Digest, my main blog.

IEEE P1581 working group publishes new white paper
The IEEE P1581 working group is defining a low overhead design-for-test (DFT) methodology to be implemented in memory devices for the support of board- and system-level connectivity test.

Synopsys TetraMAX Diagnostics for Rapid Yield Learning Adopted By UMC
TetraMAX Diagnostics Now Key Ingredient of Yield Learning Systems for Nanometer Processes

Teradyne Introduces the J750Ex: the Next-Generation of Low-Cost Test
Teradyne, Inc., a world leader in high efficiency, low-cost test, will unveil and demonstrate for the first time the new J750Ex(TM) that delivers a step function improvement in throughput and test economics.

LogicVision Expands Presence in Japan with the Addition of Noah Corporation as Distributor in Japan
LogicVision, Inc., a leading provider of test and yield learning capabilities,
today announced the addition of Noah Corporation as distributor for LogicVision products in Japan.

Design-for-Test News - Week 2, March 2007

2007-03-15T00:06:00.000-07:00

Here's a wrap up of some news items that have come across my desk this week. If you want to explore some 'off-the-beaten-track' issues regarding DFT - go to DFT Digest, my main blog.

Synopsys DFT MAX Cuts Test Costs 90 Percent in Actions Semiconductor Designs
http://www.synopsys.com/news/announce/press2007/snps_dft_max_pr.html

CheckSum Teams With Corelis to Deliver Integrated, Low-Cost Boundary-Scan Test
http://www.corelis.com/news/pr-CheckSum.htm

ISQED'07 Addresses Quality Design Challenges, Trends, and Proven Techniques with Over 100 Paper Presentations
http://digital50.com/news/items/BW/2001/07/14/20070312005386/isqed07-addresses-quality-design-challenges-trends-and-proven-techniques-with-over.html

Boundary-Scan Tools Extend Beyond Basic PCB Testing
http://www.pcb007.com/anm/templates/article.aspx?articleid=14940&zoneid=121&v=

GOEPEL Electronic Introduces New Series Of PXI Controllers
http://www.testandmeasurement.com/read/sp20070315/635948

ICCAD Call for Papers
http://edablog.com/2007/03/14/iccad-papers/

Boundary Scan Test for FPGA-Based Embedded Design
http://www.esemagazine.com/index.php?option=com_content&task=view&id=232&Itemid=2

Design-for-Test News, week 1, March 2007

2007-03-09T14:19:00.000-08:00

Here's a wrap up of some news items that have come across my desk this week. I will begin posting them as I get them. If you want to explore some 'off-the-beaten-track' issues regarding DFT - go to DFT Digest, my main blog.

Optimizing Compression
In the 1990s, Carnegie Mellon researchers created a comprehensive scan-test cost model that demonstrated how design for test (DFT) contributes to profitability. With scan compression in wide use, it is time for a new economic model, ...
TMWorld Articles - http://www.reed-electronics.com/tmworld

Synopsys DFT MAX Cuts Test Costs 90 Percent in Actions Semiconductor Designs
DFT MAX Reduces Test Data Volume and Test Application Time for High-Quality Testing MOUNTAIN VIEW, Calif., March 6 /PRNewswire-FirstCall/ -- Syno.
EDACafe.com CorpNews - http://www.edacafe.com

Boundary Scan Platform SCANFLEX® with New Controllers for Highly Complex PXI Systems
During the Boundary Scan Day® UK GOEPEL electronic, world-wide leading vendor of JTAG/Boundary Scan solutions compliant with IEEE Std. 1149.x, ...

Boundary Scan Platform SCANFLEX® with New Controllers for Highly Complex PXI Systems

Boundary Scan Support Speeds Board Design
(March 7, 2007) DALLAS — Corelis, Inc., released a boundary scan interconnect test support capability for Blackhawk XDS560-class JTAG emulators. ...
Boundary Scan Support Speeds Board Design

A.T.E. Solutions to Present Course
... Automatic Test Equipment (ATE), Design for Testability (DFT) and Built-In Self-Test (BIST) before an audience consisting of both engineers and managers. ...
ATE Solutions to present course

The New Blogger!

2007-03-09T12:27:00.000-08:00

I should write something new here. I haven't posted to this blog since before Google took over!

So here it is: I'll write from time to time here, and mention things that I'm writing over at DFT Digest. That's where the real work is. I'd like to maintain this blog as a satellite (as I've mentioned before). Also, please, if you get a chance, go and visit Design-for-Test.com. This guy's got a great site, and a good place to ask design for test questions...

Happy DFTing...
John

Countdown to ITC... and M has overshadowed T

2006-10-16T21:46:00.000-07:00

A week from today, and ITC will be kicked off in Santa Clara, CA. I'll be in attendance - specifically, sitting in a tutorial about DF... wait for it ... M! Marketing, Manufacturing, Moola, it doesn't matter, whatever it is, it is driving the forecast for the EDA industry for the next couple of years. See this item in todays on-line version of EE Times, and more of my take over at DFT Digest!

Hmmm... Maybe Something Different...

2006-10-06T17:43:00.000-07:00

... than just a blog satellite. My other blog, DFT Digest, is a place where I discuss technology, methodology and best-practices of DFT. It's not a place that I really want to do much of the "news-link" type of blogging.

Perhaps this blog is where I should do that....??

First BlogSpot post for DFT Digest

2006-09-11T22:00:00.000-07:00

This is a satellite to the original DFT Digest