Design-for-Test News - Week 3, March 2007

Here's a wrap up of some news items that have come across my desk this week. If you want to explore some 'off-the-beaten-track' issues regarding DFT - go to DFT Digest, my main blog.

IEEE P1581 working group publishes new white paper
The IEEE P1581 working group is defining a low overhead design-for-test (DFT) methodology to be implemented in memory devices for the support of board- and system-level connectivity test.

Synopsys TetraMAX Diagnostics for Rapid Yield Learning Adopted By UMC
TetraMAX Diagnostics Now Key Ingredient of Yield Learning Systems for Nanometer Processes

Teradyne Introduces the J750Ex: the Next-Generation of Low-Cost Test
Teradyne, Inc., a world leader in high efficiency, low-cost test, will unveil and demonstrate for the first time the new J750Ex(TM) that delivers a step function improvement in throughput and test economics.

LogicVision Expands Presence in Japan with the Addition of Noah Corporation as Distributor in Japan
LogicVision, Inc., a leading provider of test and yield learning capabilities,
today announced the addition of Noah Corporation as distributor for LogicVision products in Japan.

Design-for-Test News - Week 2, March 2007

Here's a wrap up of some news items that have come across my desk this week. If you want to explore some 'off-the-beaten-track' issues regarding DFT - go to DFT Digest, my main blog.

Synopsys DFT MAX Cuts Test Costs 90 Percent in Actions Semiconductor Designs
http://www.synopsys.com/news/announce/press2007/snps_dft_max_pr.html

CheckSum Teams With Corelis to Deliver Integrated, Low-Cost Boundary-Scan Test
http://www.corelis.com/news/pr-CheckSum.htm

ISQED'07 Addresses Quality Design Challenges, Trends, and Proven Techniques with Over 100 Paper Presentations
http://digital50.com/news/items/BW/2001/07/14/20070312005386/isqed07-addresses-quality-design-challenges-trends-and-proven-techniques-with-over.html

Boundary-Scan Tools Extend Beyond Basic PCB Testing
http://www.pcb007.com/anm/templates/article.aspx?articleid=14940&zoneid=121&v=

GOEPEL Electronic Introduces New Series Of PXI Controllers
http://www.testandmeasurement.com/read/sp20070315/635948

ICCAD Call for Papers
http://edablog.com/2007/03/14/iccad-papers/

Boundary Scan Test for FPGA-Based Embedded Design
http://www.esemagazine.com/index.php?option=com_content&task=view&id=232&Itemid=2

Design-for-Test News, week 1, March 2007

Here's a wrap up of some news items that have come across my desk this week. I will begin posting them as I get them. If you want to explore some 'off-the-beaten-track' issues regarding DFT - go to DFT Digest, my main blog.

Optimizing Compression
In the 1990s, Carnegie Mellon researchers created a comprehensive scan-test cost model that demonstrated how design for test (DFT) contributes to profitability. With scan compression in wide use, it is time for a new economic model, ...
TMWorld Articles - http://www.reed-electronics.com/tmworld

Synopsys DFT MAX Cuts Test Costs 90 Percent in Actions Semiconductor Designs
DFT MAX Reduces Test Data Volume and Test Application Time for High-Quality Testing MOUNTAIN VIEW, Calif., March 6 /PRNewswire-FirstCall/ -- Syno.
EDACafe.com CorpNews - http://www.edacafe.com

Boundary Scan Platform SCANFLEX® with New Controllers for Highly Complex PXI Systems
During the Boundary Scan Day® UK GOEPEL electronic, world-wide leading vendor of JTAG/Boundary Scan solutions compliant with IEEE Std. 1149.x, ...

Boundary Scan Platform SCANFLEX® with New Controllers for Highly Complex PXI Systems

Boundary Scan Support Speeds Board Design
(March 7, 2007) DALLAS — Corelis, Inc., released a boundary scan interconnect test support capability for Blackhawk XDS560-class JTAG emulators. ...
Boundary Scan Support Speeds Board Design

A.T.E. Solutions to Present Course
... Automatic Test Equipment (ATE), Design for Testability (DFT) and Built-In Self-Test (BIST) before an audience consisting of both engineers and managers. ...
ATE Solutions to present course

The New Blogger!

I should write something new here. I haven't posted to this blog since before Google took over!

So here it is: I'll write from time to time here, and mention things that I'm writing over at DFT Digest. That's where the real work is. I'd like to maintain this blog as a satellite (as I've mentioned before). Also, please, if you get a chance, go and visit Design-for-Test.com. This guy's got a great site, and a good place to ask design for test questions...

Happy DFTing...
John