Design-for-Test News, week 1, March 2007

Here's a wrap up of some news items that have come across my desk this week. I will begin posting them as I get them. If you want to explore some 'off-the-beaten-track' issues regarding DFT - go to DFT Digest, my main blog.

Optimizing Compression
In the 1990s, Carnegie Mellon researchers created a comprehensive scan-test cost model that demonstrated how design for test (DFT) contributes to profitability. With scan compression in wide use, it is time for a new economic model, ...
TMWorld Articles - http://www.reed-electronics.com/tmworld

Synopsys DFT MAX Cuts Test Costs 90 Percent in Actions Semiconductor Designs
DFT MAX Reduces Test Data Volume and Test Application Time for High-Quality Testing MOUNTAIN VIEW, Calif., March 6 /PRNewswire-FirstCall/ -- Syno.
EDACafe.com CorpNews - http://www.edacafe.com

Boundary Scan Platform SCANFLEX® with New Controllers for Highly Complex PXI Systems
During the Boundary Scan Day® UK GOEPEL electronic, world-wide leading vendor of JTAG/Boundary Scan solutions compliant with IEEE Std. 1149.x, ...

Boundary Scan Platform SCANFLEX® with New Controllers for Highly Complex PXI Systems

Boundary Scan Support Speeds Board Design
(March 7, 2007) DALLAS — Corelis, Inc., released a boundary scan interconnect test support capability for Blackhawk XDS560-class JTAG emulators. ...
Boundary Scan Support Speeds Board Design

A.T.E. Solutions to Present Course
... Automatic Test Equipment (ATE), Design for Testability (DFT) and Built-In Self-Test (BIST) before an audience consisting of both engineers and managers. ...
ATE Solutions to present course