Thursday, March 15, 2007

Design-for-Test News - Week 2, March 2007

Here's a wrap up of some news items that have come across my desk this week. If you want to explore some 'off-the-beaten-track' issues regarding DFT - go to DFT Digest, my main blog.

Synopsys DFT MAX Cuts Test Costs 90 Percent in Actions Semiconductor Designs
http://www.synopsys.com/news/announce/press2007/snps_dft_max_pr.html

CheckSum Teams With Corelis to Deliver Integrated, Low-Cost Boundary-Scan Test
http://www.corelis.com/news/pr-CheckSum.htm

ISQED'07 Addresses Quality Design Challenges, Trends, and Proven Techniques with Over 100 Paper Presentations
http://digital50.com/news/items/BW/2001/07/14/20070312005386/isqed07-addresses-quality-design-challenges-trends-and-proven-techniques-with-over.html

Boundary-Scan Tools Extend Beyond Basic PCB Testing
http://www.pcb007.com/anm/templates/article.aspx?articleid=14940&zoneid=121&v=

GOEPEL Electronic Introduces New Series Of PXI Controllers
http://www.testandmeasurement.com/read/sp20070315/635948

ICCAD Call for Papers
http://edablog.com/2007/03/14/iccad-papers/

Boundary Scan Test for FPGA-Based Embedded Design
http://www.esemagazine.com/index.php?option=com_content&task=view&id=232&Itemid=2

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