The International Test Conference is now recent history - but here are a few related news items and press releases that have come out in the past week. For discussion and/or analysis, please visit DFT Digest or DFT Forum!
Intellitech Offers New Concurrent JTAG Test Platform for PCBs with ARM Based Processors
Panel explores the expanded role of test in DFM
Intel VP at ITC calls for test development advances to meet challenges of next-gen SoC
The Last Bastion II : Some Q&A with DeFacto President and CTO Dr. Chouki Aktouf
ATPG Tool Meets Growing Demand For Scan Test Compression
TI fellow defines conditions and requirements for adaptive test at ITC
LogicVision Common Stock Transferred to the Nasdaq Capital Market
LogicVision Reports Third Quarter 2007 Financial Results
DFT Microsystems Bolsters Executive Team
Synopsys Customers Accelerate Yield Learning With Converged Test and Yield Management Data Flow
Saturday, October 27, 2007
Tuesday, October 23, 2007
International Test Conference Begins!
A couple more press releases for Day 3 of the International Test Conference (ITC). Today the technical program starts (yesterday and Sunday were filled with day-long tutorials). Go to the main DFT Digest site for some insight into what's happening, or add your two cents at the DFT Forum!
G2 Microsystems Innovates With Cadence Low-Power Solution for Faster Development of Wireless Devices
Aehr Test Systems Announces FOX-15(TM) Full Wafer Contact Test and Burn-In System
ASSET® Expands Next-Generation Embedded Instrumentation
Cadence Test Technology Helps LSI Corporation, Kawasaki Microelectronics Deliver Products Faster
Cadence Encounter Test Helps Enable IBM To Deliver High-volume Chips
Genesys Testware Adds Automated Batch-mode Diagnosis and Characterization of Embedded Memories
G2 Microsystems Innovates With Cadence Low-Power Solution for Faster Development of Wireless Devices
Aehr Test Systems Announces FOX-15(TM) Full Wafer Contact Test and Burn-In System
ASSET® Expands Next-Generation Embedded Instrumentation
Cadence Test Technology Helps LSI Corporation, Kawasaki Microelectronics Deliver Products Faster
Cadence Encounter Test Helps Enable IBM To Deliver High-volume Chips
Genesys Testware Adds Automated Batch-mode Diagnosis and Characterization of Embedded Memories
Monday, October 22, 2007
ITC Monday news...
Posting these as they come up...
DeFacTo Unveils New Design for Test Product that Eliminates Need for Gate-level Scan; Creates Industry’s First High-level DFT Sign-off Methodology
Synopsys Advances Low Power Management for Manufacturing Test
Synopsys Improves the Quality of Manufacturing Tests with Timing-Aware Pattern Generation
DeFacTo Unveils New Design for Test Product that Eliminates Need for Gate-level Scan; Creates Industry’s First High-level DFT Sign-off Methodology
Synopsys Advances Low Power Management for Manufacturing Test
Synopsys Improves the Quality of Manufacturing Tests with Timing-Aware Pattern Generation
Sunday, October 21, 2007
ITC month, weeks 2 and 3
A couple of things:
ITC Test week started today with tutorials. Hop on over to DFT Digest for additional coverage of this event.
Speaking of DFT Digest, there has begun a collaboration of sorts between DFT Digest and DFT Forum. DFT Digest will still try to present interesting DFT-related information, while DFT Forum will be the main place for DFT- and EDA-related real-time discussion. Please visit and register for both sites!
Now, following are some of the happenings in the DFT world for the second couple of weeks of October:
STC Releases First Draft of Terminology Specifications to Semiconductor Industry and Announces Activities at ITC
Magma Unveils Talus ATPG and Talus ATPG-X - Expands Design-for-Test Capabilities with Physically Aware ATPG and On-Chip Compression
Magma Partners with Inovys and Source III to Ensure Interoperability of Talus ATPG and Leading Testers
LogicVision Announces Industry's Most Comprehensive On-Chip eDRAM Test and Repair Solution
LogicVision Receives Letter From Nasdaq Regarding Noncompliance With Minimum Bid Price Rule
Perform Design-for-Test and Power Management at the RTL
Mentor Graphics Announces TestKompress Xpress Technology to Address Manufacturing Test Requirements for 65 and 45 Nanometer Integrated Circuits
ITC Test week started today with tutorials. Hop on over to DFT Digest for additional coverage of this event.
Speaking of DFT Digest, there has begun a collaboration of sorts between DFT Digest and DFT Forum. DFT Digest will still try to present interesting DFT-related information, while DFT Forum will be the main place for DFT- and EDA-related real-time discussion. Please visit and register for both sites!
Now, following are some of the happenings in the DFT world for the second couple of weeks of October:
STC Releases First Draft of Terminology Specifications to Semiconductor Industry and Announces Activities at ITC
Magma Unveils Talus ATPG and Talus ATPG-X - Expands Design-for-Test Capabilities with Physically Aware ATPG and On-Chip Compression
Magma Partners with Inovys and Source III to Ensure Interoperability of Talus ATPG and Leading Testers
LogicVision Announces Industry's Most Comprehensive On-Chip eDRAM Test and Repair Solution
LogicVision Receives Letter From Nasdaq Regarding Noncompliance With Minimum Bid Price Rule
Perform Design-for-Test and Power Management at the RTL
Mentor Graphics Announces TestKompress Xpress Technology to Address Manufacturing Test Requirements for 65 and 45 Nanometer Integrated Circuits
Tuesday, October 09, 2007
Wednesday, October 03, 2007
Design-for-Test In the News
A smattering of press releases and such for the last couple of months:
Westinghouse Rail Systems selects XJTAG boundary scan system to verify prototype integrity
Mentor Graphics Chairman and CEO to Present Keynote at International System-on-Chip Design Conference
Mentor's TestKompress reaches out to 45-nm
Mentor Graphics Announces TestKompress Xpress Technology to Address Manufacturing Test Requirements for 65 and 45 Nanometer Integrated Circuits
LogicVision Announces That Q3 2007 Cash Exceeds Guidance
Goepel’s Puri on North American restructuring
Dr. Jacob Abraham receives Best Paper Award at international conference
Global Unichip Adopts Synopsys Test Solution to Achieve Higher SoC Test Quality
Strategic Alliance Between GOEPEL Electronic And Testonica Lab
LogicVision Provides Desktop Silicon Characterization and Diagnostics Solution with the Introduction of Silicon Insight
Perform Design-for-Test and Power Management at the RTL
New Digital I/O Scan Test Module Provides Flexibility
International Test Conference -- The Cornerstone of Test Week(TM) Holds 38th Conference in Santa Clara, California, October 23-25, 2007
ITC tackles nanometer test challenges
Synopsys Lowers the Cost of Semiconductor Testing at Tessolve
Cost-Effective, Ultra-High-Quality Test Results Using Synopsys DFT MAX Achieved at SHARP
ARM Selects XJTAG For RealView Development Tools Debug And Test
LogicVision Announces New Release of Its Embedded SerDes Test Solution
SynTest granted 6 more Patents since October 2006
Westinghouse Rail Systems selects XJTAG boundary scan system to verify prototype integrity
Mentor Graphics Chairman and CEO to Present Keynote at International System-on-Chip Design Conference
Mentor's TestKompress reaches out to 45-nm
Mentor Graphics Announces TestKompress Xpress Technology to Address Manufacturing Test Requirements for 65 and 45 Nanometer Integrated Circuits
LogicVision Announces That Q3 2007 Cash Exceeds Guidance
Goepel’s Puri on North American restructuring
Dr. Jacob Abraham receives Best Paper Award at international conference
Global Unichip Adopts Synopsys Test Solution to Achieve Higher SoC Test Quality
Strategic Alliance Between GOEPEL Electronic And Testonica Lab
LogicVision Provides Desktop Silicon Characterization and Diagnostics Solution with the Introduction of Silicon Insight
Perform Design-for-Test and Power Management at the RTL
New Digital I/O Scan Test Module Provides Flexibility
International Test Conference -- The Cornerstone of Test Week(TM) Holds 38th Conference in Santa Clara, California, October 23-25, 2007
ITC tackles nanometer test challenges
Synopsys Lowers the Cost of Semiconductor Testing at Tessolve
Cost-Effective, Ultra-High-Quality Test Results Using Synopsys DFT MAX Achieved at SHARP
ARM Selects XJTAG For RealView Development Tools Debug And Test
LogicVision Announces New Release of Its Embedded SerDes Test Solution
SynTest granted 6 more Patents since October 2006
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